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DeMon48_128k

Intel 8049 (8048, 8748, 8749, 8035, 8039) / MCS-48 Hardware-Debugger & Monitor

Documentation - Contents

Contents - Chapter 1 - Chapter 2 - Chapter 3 - Chapter 4 - Chapter 5 - Chapter 6 - Chapter 7 - Drawings - Project page (de)

  • 1.0.0 Why the DeMon48 project was created
    • 1.1.0 First contact with MCS-48
  • 2.0.0 MCS-48 Primer
    • 2.1.0 The MCS-48 microcontroller family
      • 2.1.1 Types and on-chip resources (1979)
      • 2.1.2 MCS-48 in publications of the 1970s and 1980s
    • 2.2.0 The MCS-48 microcontrollers
      • 2.2.1 Program memory
      • 2.2.2 Reset- and Interrupt-Vectors
      • 2.2.3 PSW (Program Status Word)
      • 2.2.4 Internal RAM
      • 2.2.5 Stack in internal RAM
      • 2.2.6 Timer/Counter
    • 2.3.0 Minimal system with external program memory
    • 2.4.0 DIP40 pin assignment, control signals, ports, timing
      • 2.4.1 EA
      • 2.4.2 *RESET
      • 2.4.3 *INT
      • 2.4.4 ALE
      • 2.4.5 *PSEN
      • 2.4.6 *RD
      • 2.4.7 *WR
      • 2.4.8 PROG
      • 2.4.9 P1, P2
      • 2.4.10 BUS
      • 2.4.11 Timing
    • 2.5.0 Logic-Analyzer Traces
  • 3.0.0 MCS-48 in the 21st century
    • 3.1.0 First power-up
    • 3.2.0 NOP-Loop
    • 3.3.0 Program- and data-memory in a single RAM
    • 3.4.0 Debug-µC
      • 3.4.1 NOP-Loop with Debug-µC
      • 3.4.2 256Byte-Page Write with Debug-µC
    • 3.5.0 Single-Step Hardware
    • 3.6.0 DeMon48_128k Memory organization / MMU
      • 3.6.1 DBR - Data Bank Register
      • 3.6.2 PBR - Program Bank Register
      • 3.6.3 Using "8243" port expanders
      • 3.6.4 DA16 - Data Address 16
      • 3.6.5 Expansion Register
      • 3.6.6 Accessing the MMU
      • 3.6.7 Composition of the address in different situations
      • 3.6.8 Memory-Mapped I/O
    • 3.7.0 Hardware-Breakpoint
    • 3.8.0 Clock generation and input for external clock
  • 4.0.0 The monitor software: "God Mode" for the developer
    • 4.1.0 Monitor-Call
      • 4.1.1 Read PC, PBR, DBR
      • 4.1.2 Monitor-Start
      • 4.1.3 Interrupt detection
      • 4.1.4 "Pending Bank Switch" detection
      • 4.1.5 Read A, T, PSW, R0
      • 4.1.6 Read P1, P2, T0, T1, *INT, F1
      • 4.1.7 Read internal RAM
      • 4.1.8 Modify Stack
    • 4.2.0 Monitor Meta-state
    • 4.3.0 Monitor-Exit
      • 4.3.1 Write back saved and changed contents
      • 4.3.2 Write to internal RAM
      • 4.3.3 Write to PBR, DBR, P1, P2 and F1
      • 4.3.4 Restore R0, PSW, T and A
      • 4.3.5 Modify Stack
      • 4.3.6 Restore PC, timer/counter configuration and MB-FF
  • 5.0.0 Memory configurations
    • 5.1.0 Jumper
    • 5.2.0 DA16 (Data Address 16)
    • 5.3.0 Modes
    • 5.4.0 Memory Maps
      • 5.4.1 Memory Map 1
      • 5.4.2 Memory Map 2
      • 5.4.3 Memory Map 3
      • 5.4.4 Memory Map 4
      • 5.4.5 Memory Map 5
      • 5.4.6 Memory Map 6
  • 6.0.0 GUI / Windows-Software
    • 6.1.0 Status-Indicators
    • 6.2.0 Aux-/CPU-Registers & Ports
    • 6.3.0 External RAM (Program/Data)
    • 6.4.0 Internal RAM (Data)
    • 6.5.0 'File' button
    • 6.6.0 'AS' button
    • 6.7.0 'ROM' button
    • 6.8.0 'Fill' button
    • 6.9.0 Project-Configuration
    • 6.10.0 'Run' button
    • 6.11.0 'Step' button
    • 6.12.0 'Sync' button
    • 6.13.0 'Reset' button
    • 6.14.0 'Mon.Entry' and 'Mon.Exit' options
    • 6.15.0 'Auto' button
    • 6.16.0 Software-Breakpoint
    • 6.17.0 Hardware-Breakpoint
    • 6.18.0 Stopwatch
  • 7.0.0 Appendix
    • 7.1.0 Instruction set of the 8035,8039,8048,8049,8748,8749,8040,8050µCs
    • 7.2.0 DeMon48_128k code example "RAM Test"

Contents - Chapter 1 - Chapter 2 - Chapter 3 - Chapter 4 - Chapter 5 - Chapter 6 - Chapter 7 - Drawings - Project page (de)
DeMon48_128k_Documentation - Onlineversion - ©2023,2024 Marco Schmoll * www.controller-designs.de * All Rights Reserved !
DeMon48_128k * Intel 8049 / MCS-48 Hardware-Debugger & Monitor - ©2021...2024 Marco Schmoll * www.controller-designs.de * All Rights Reserved !
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