DeMon48_128k

4.0.0 The monitor software: "God Mode" for the developer

By using small MCS-48 programs that are loaded into the external RAM by the Debug-µC's firmware and executed by the MCS-48 µC under supervision of the Debug-µC, it was possible to create a monitor and debug system that does not block any on-chip resources of the MCS-48 µC or leave them in a changed state after exiting the monitor software.

Basically, the execution of individual commands of the MCS-48 user program under supervision of the debugger with visualization in the GUI takes place in three phases:

1. Reading the state of the MMU and saving the internal registers of the MCS-48 µC
   (DBR, PBR, PC, A, T, PSW, R0)
2. Reading the status of the ports, the user flag1, the test and interrupt inputs
   (P1, P2, F1, T0, T1, *INT)
3. Read the internal RAM of the MCS-48 µC
4. Upload all read values to the Windows GUI

• The MCS-48 µC is stopped and the user can edit the contents of PC, A, PSW, internal registers, internal/external RAM, ports, etc. in the Windows GUI.
• If the user triggers the execution of the next instruction by clicking the corresponding button in the GUI, the monitor is exited and the next instruction in the MCS-48 user program is executed:

1. Download external RAM memory areas changed in the GUI
2. Download internal RAM memory areas changed in the GUI
3. Download register contents changed in the GUI
4. Restore the registers in the MCS-48 µC
5. Restore the MCS-48 µC's program counter (PC)
6. Execute the next command
7. Jump to : I. Monitor call

While the monitor is active and monitor routines are executed, the MCS-48 µC has at maximum control over the lower 8 address lines A0 to A7.

DThe address line A8, which is used by the MCS-48 µC to switch between 256 bytes of debug program-memory and 256 bytes of debug data-memory while the monitor is active, is connected to the *PSEN signal via the MMU. The other address signals A9 to A16 are provided by the Debug-µC.

4.1.0 Monitor-Call

When the monitor software is called, it checks whether the execution of the MCS-48 user program by the MCS-48 µC has already been stopped and the single-step hardware is active. If not, the single-step hardware is activated and the Debug-µC waits for the MCS-48 µC to process all instruction cycles belonging to the currently executed instruction.

4.1.1 Read PC, PBR, DBR

The program counter's contents, which is output by the MCS-48 µC at BUS and P2.0 to P2.3, is read and saved as DBG_ReturnAddress.

In the same step, the contents of the Program Bank Register (PBR, consisting of PBR1 and PBR2) and Data Bank Register (DBR) are read and saved.

4.1.2 Monitor-Start

1. Load and execute (without prior check for hardware interrupt (*)):
   
   $   04 JMP 009
   $+1 09
   ($ = lower 8 bits of the PC (Program Counter))
2. Load:
   
   09 00/65 NOP / STOP TCNT
   0A 04    JMP 009
   0B 09
   
   If the monitor option "STOP TCNT" (Stop Timer / Counter) is selected in the GUI, the firmware in the Debug-µC inserts the corresponding opcode (0x65) in address 0x09, otherwise the one for "NOP" (0x00).
3. Execute instructions in addresses 0x09 to 0x0B
4. If a new IRQ was detected before executing any of the commands in addresses 0x09 to 0x0B:
   1. PCL = 0x09
   2. Re-execute instructions in addresses 0x09 to 0x0B

(*) If an interrupt was triggered during the execution of the previous MCS-48 instruction, the return address in the MCS-48 user program is already correctly stored as one of the interrupt vectors.

4.1.3 Interrupt detection

While the MCS-48 µC executes one of the monitor programs, timer/counter interrupts and external interrupt requests have to be detected because these cause a return address within one of the monitor programs to be stored on the stack of the MCS-48 µC and the return address in the MCS-48 user program does not point to the corresponding interrupt vector.

The Debug-µC detects interrupts by checking the address bus of the MCS-48 µC for the interrupt vectors 0x003 and 0x007 before executing each MCS-48 command following the first "JMP 009" instruction (see "4.1.2 Monitor Start").

If an interrupt has been detected the stack of the MCS-48 µC is manipulated after the PSW has been saved in such a way that the return address within one of the monitor programs stored there is replaced by the return address in the MCS-48 user program and the correct interrupt vector, depending on the source of the interrupt request, is stored in the Debug-µC as the return address in the MCS-48 user program.

In addition, the lower 8 bits of the program counter (PCL) are set to the start address of the current monitor program by a "JMP 009" instruction.

4.1.4 "Pending Bank Switch" detection

The Debug-µC must determine whether a bank change has been prepared using "SEL MB0" or "SEL MB1" in the MCS-48 user program, but has not yet become effective as Bit11 of the PC by execution of a JMP or CALL command ("Pending Bank Switch").

This happens after the MCS-48 µC has executed the first "JMP 009" instruction. A change to the lower program-memory bank was prepared if bit 11 was set when the MCS-48 address bus was read for the first time and was reset after executing the unconditional jump command, a change to the upper program-memory bank was prepared if bit 11 was reset when the address bus was read for the first time and was set after executing the unconditional jump instruction.

The detection of a "Pending Bank Switch" and the correct recovery by the debugger firmware works in conjunction with interrupts as well, since no check for a "Pending Bank Switch" is carried out if an interrupt was detected after the execution of the first "JMP 009" instruction and before the execution of the following instruction. In this case, the state of the MB-FF is not manipulated when exiting the monitor, which is only necessary if bit 11 of the program counter has to be returned to the state before executing the monitor routines. All 12 bits of the program counter of the MCS-48 µC are correctly restored by the "RETR" instruction at the end of the interrupt service routine in the MCS-48 user program and the MB-FF was not changed by the monitor software.

If a "Pending Bank Switch" is detected, the currently active memory bank in the MCS-48 user program is selected when exiting the monitor and the preparation flip-flop (MB-FF) is set to the state before the monitor software was called.

4.1.5 Read A, T, PSW, R0

The contents of the accumulator (A), the timer/counter register (T) and the "Program Status Word" (PSW) are saved by keeping address lines A0 to A7 and A9 to A16 at the value 0x1FE09 during the execution of the "MOVX @R0,A" instruction loaded in address 0x09 of the debug program-memory by the Debug-µC, so that, regardless of the previously unknown contents of the R0 (R0') register, the accumulator contents of the MCS-48 µC are written to address 0x09 in the debug data-memory. A8 remains under the control of the MCS-48 µC via the MMU, as it is required to switch between the debug program-memory and the debug data-memory. In the same way, the contents of R0 are then saved in register bank 0 and at the end of this routine an index register is finally available whose contents can be destroyed without causing any damage - for example for use in a "MOVX @Ri,A" instruction.

Load:

Read Accumulator

1. MCS-48 µC controls D0 to D7, A8, *RAM_OE, *RAM_WE
   Debugger controls A0 to A7, A9 to A16
   A0 to A7, A9 to A16 = 0x1FE09
2. Execute instruction in address 0x09 (MOVX @R0,A)
   The accumulator contents are stored in address 0x1FF09 of the debugger RAM
3. If a new IRQ was detected before executing the instruction in address 0x09:
   1. PCL = 0x09
   2. Execute instruction in address 0x09
4. Read address 0x1FF09 (accumulator contents) and save as DBG_A

Read T-Register

1. MCS-48 µC controls A0 to A7, D0 to D7, *RAM_OE, *RAM_WE
2. Execute commands in addresses 0x0A (MOV A,T) to 0x0D (JMP 009):
   Afterwards A contains the contents of the T register
3. If a new IRQ was detected before executing any of the instructions in addresses 0x0A to 0x0D:
   1. PCL = 0x09
   2. Re-execute instructions in addresses 0x09 to 0x0D
4. MCS-48 µC controls D0 to D7, A8, *RAM_OE, *RAM_WE
   Debugger controls A0 to A7, A9 to A16
   A0 to A7, A9 to A16 = 0x1FE09
5. Execute command at address 0x09 (MOVX @R0,A)
   The accumulator contents (=T register) are stored in address 0x1FF09 of the debug RAM
6. Read address 0x1FF09 (T register) and save as DBG_T
7. If a new IRQ was detected before executing the instruction in address 0x09:
   1. PCL = 0x09
   2. Execute instruction in address 0x09
   3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T

Read PSW

1. Store opcode for "MOV A,PSW" (0xC7) in address 0x0A:
   
   09 90 MOVX @R0,A ;Put A in 0x1FF09
   0A C7 MOV A,PSW
   0B 00 NOP
   0C 04 JMP 009
   0D 09
2. MCS-48 µC controls A0 to A7, D0 to D7, *RAM_OE, *RAM_WE
3. Execute instructions in addresses 0x0A (MOV A,PSW) to 0x0D (JMP 009):
   Afterwards A contains the contents of the PSW
4. If a new IRQ was detected before executing any of the instructions in addresses 0x0A to 0x0D:
   1. PCL = 0x09
   2. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
   3. Re-execute instructions in addresses 0x09 to 0x0D
5. MCS-48 µC controls D0 to D7, A8, *RAM_OE, *RAM_WE
   Debugger controls A0 to A7, A9 to A16
   A0 to A7, A9 to A16 = 0x1FE09
6. Execute instruction in address 0x09 (MOVX @R0,A)
   The accumulator contents (=PSW) are stored in address 0x1FF09 of the debug RAM
7. Read address 0x1FF09 (PSW) and save as DBG_PSW
8. If a new IRQ was detected before executing the instruction in address 0x09:
   1. PCL = 0x09
   2. Execute instruction in address 0x09
   3. Increment StackPointer in DBG_PSW
   4. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T

Read R0RB0 (R0 in Register Bank 0)

1. Since the contents of the PSW and thus the bit for selecting the active register bank, "BS", are now saved, the contents of the PSW can be destroyed by explicitly selecting register bank 0.
   Store opcode for "SEL RB0" (0xC5) in address 0x0A and opcode for "MOV A,R0" (0xF8) in address 0x0B:
   
   09 90 MOVX @R0,A ;Put A in 0x1FF09
   0A C5 SEL RB0
   0B F8 MOV A,R0
   0C 04 JMP 009
   0D 09
2. MCS-48 µC controls A0 to A7, D0 to D7, *RAM_OE, *RAM_WE
3. Execute commands in addresses 0x0A (SEL RB0) to 0x0D (JMP 009):
   Afterwards A contains the contents of register R0 in register bank 0
4. If a new IRQ was detected before executing any of the instructions in addresses 0x0A to 0x0D:
   1. PCL = 0x09
   2. Increment StackPointer in DBG_PSW
   3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
   4. Re-execute instructions in addresses 0x09 to 0x0D
5. MCS-48 µC controls D0 to D7, A8, *RAM_OE, *RAM_WE
   Debugger controls A0 to A7, A9 to A16
   A0 to A7, A9 to A16 = 0x1FE09
6. Execute command in address 0x09 (MOVX @R0,A)
   The accumulator contents (=R0, RB0) are stored in address 0x1FF09 of the debug RAM
7. Adresse 0x1FF09 (R0, RB0) lesen und als DBG_R0RB0 sichern
8. If a new IRQ was detected before executing the instruction in address 0x09:
   1. PCL = 0x09
   2. Execute instruction in address 0x09
   3. Increment StackPointer in DBG_PSW
   4. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T

Set PCL to 0x09

1. Execute commands in addresses 0x0A to 0x0D to set the lower 8 bits of the program counter (PCL) to 0x09
2. If a new IRQ was detected before executing any of the instructions in addresses 0x0A to 0x0D:
   1. PCL = 0x09
   2. Increment StackPointer in DBG_PSW
   3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T

4.1.6 Read P1, P2, T0, T1, *INT, F1

The state of P1, P2, F1 and the T0, T1 and *INT inputs are read and stored in the debug data area.

Load:

After executing the instructions in addresses 0x09 to 0x29, the lower 8 bits of the program counter (PCL) contain 0x09 and the contents of P1 can be read from RAM address 0x1FF00, the contents of P2 from RAM address 0x1FF01 and the state of *INT (bit3), F1 (user flag 1) (bit2), T1 (bit1) and T0 (bit0) from RAM address 0x1FF02.

If a new IRQ was detected before executing any of the commands in addresses 0x09 to 0x29:

1. PCL = 0x09
2. Increment StackPointer in DBG_PSW
3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
4. Re-execute instructions in addresses 0x09 to 0x29

4.1.7 Read internal RAM

The MCS-48 code for copying the internal RAM (address 0x01 to 0x7F, address 0x00 has already been saved with R0, RB0 as DBG_R0RB0) is loaded into the external debug RAM.

Load:

After executing the commands in addresses 0x09 to 0x10, the lower 8 bits of the program counter (PCL) contain 0x09 and the contents of the internal RAM from address 0x01 to address 0x7F can be read from addresses 0x1FF01 to 0x1FF7F of the debug data area in the external RAM.

If a new IRQ was detected before executing one of the instructions in addresses 0x09 to 0x10:

1. PCL = 0x09
2. Increment StackPointer in DBG_PSW
3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
4. Re-execute instructions in addresses 0x09 to 0x10

4.1.8 Modify Stack

If a timer/counter interrupt or an extermal interrupt request is detected during the execution of the previous MCS-48 programs and the stack has not yet been modified, this routine is executed.

Load:

After loading the program code, the Debug-µC inserts the calculated address (StackIndex = (StackPointer - 1) * 2 + 8) of the lower byte of the stack memory locations to be used in address 0x0A, the low-order byte of the return address in the MCS-48 user program in address 0x0C and the remaining 4 bits of the return address in the MCS-48 user program in address 0x10 together with the high-order 4 bits of the PSW saved by the Debug-µC. Finally, the values saved by the Debug-µC for R0RB0 are loaded into address 0x13 and for the accumulator into address 0x15, since the contents of these two are destroyed by the program.

After executing the instructions in addresses 0x09 to 0x17, the correct return address including PSW bits is stored on the stack and the lower 8 bits of the program counter (PCL) contain 0x09.

During execution, no check is made for a new IRQ - it has already been detected and thus the modification of the stack has been initiated.

4.2.0 Monitor Meta-state

A kind of "meta state" is now reached in which the state of the MCS-48 µC after the last instruction in the MCS-48 user program is completely known and can be changed at will in the GUI before continuing execution of the MCS-48 user program.

4.3.0 Monitor-Exit

4.3.1 Write back saved and changed contents

The contents (registers, flags, bits) saved when the monitor is called are written back in the reverse order of how they were read. PBR, DBR, P1, P2, F1 and internal RAM are only written if they were changed by the user in the GUI or if the stack contents had to be manipulated by the debugger firmware in the debug data area. R0, PSW, A, PC, the selection of the active 2kB memory bank and the state of the MB flip-flop are always considered "destroyed" by the execution of the monitor programs, so they are written back to the MCS-48 µC, together with the T register, if the user changed its contents in the GUI, when the monitor software is exited.

4.3.2 Write to internal RAM

Load:

After the Debug-µC has loaded the program code into the debug program memory, the desired contents of the internal RAM of the MCS-48 µC into addresses 0x1FF01 to 0x1FF7F of the debug data memory and the MCS-48 µC has executed the instructions in the addresses 0x09 to 0x10, the lower 8 bits of the program counter (PCL) contain 0x09 and the addresses 0x01 to 0x07 of the internal RAM have been written with their new contents.

If a new IRQ was detected before executing one of the instructions in addresses 0x09 to 0x10:

1. PCL = 0x09
2. Increment StackPointer in DBG_PSW
3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
4. Re-execute instructions in addresses 0x09 to 0x10

4.3.3 Write to PBR, DBR, P1, P2 and F1

Load:

After loading the program code, the Debug-µC inserts the new value for P2 in address 0x0A, the new value for P1 in address 0x0D and the MCS-48 opcode for "NOP" (0x00) for a reset user flag1 (F1) in address 0x10 or "CPL F1" (0xB5) for a set user flag1 (F1) and executes the instructions in addresses 0x09 to 0x12.

Afterwards the lower 8 bits of the program counter (PCL) contain 0x09 and Port1 (P1), Port2 (P2) and User-Flag1 (F1) have adopted the new values.

If a new IRQ was detected before executing one of the instructions in addresses 0x09 to 0x12:

1. PCL = 0x09
2. Increment StackPointer in DBG_PSW
3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
4. Re-execute instructions in addresses 0x09 to 0x12

The Debug-µC can write new values for PBR and DBR of the MMU without involvement of the MCS-48 µC.

4.3.4 Restore R0, PSW, T and A

Load:

After the program code and the contents of register R0 in register bank 0 (R0, RB0) from DBG_R0RB0 in address 0x0A, the contents of the processor status word (PSW) from DBG_PSW in address 0x0C, the contents of the timer/counter register (T) from DBG_T in address 0x0F and the contents of the accumulator (A) from DBG_A in address 0x12 of the debug program memory have been loaded by the Debug-µC and the commands in addresses 0x09 to 0x14 have been executed by the MCS-48 µC, R0, PSW, T and A have adopted the values stored in the Debug-µC and the lower 8 bits of the program counter (PCL) contain 0x09. By inserting the MCS-48 opcode for "NOP" (0x00) in address 0x10, writing to the T register can be suppressed if the user has not changed the contents of the T register in the GUI.

If a new IRQ was detected before executing one of the instructions in addresses 0x09 to 0x14:

1. PCL = 0x09
2. Increment StackPointer in DBG_PSW
3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
4. Re-execute instructions in addresses 0x09 to 0x14

4.3.5 Modify Stack

See "4.1.8 Modify Stack".

4.3.6 Restore PC, timer/counter configuration and MB-FF

Load:

1. Prepare to restore bit 11 of the PC (active memory bank):
   If a "Pending SEL MB0" was detected when the monitor was started (bit 11 of the PC was set when the monitor was called and reset after an unconditional jump instruction was executed), a "SEL MB1" instruction (opcode 0xF5) is inserted in address 0x09.
   If a "Pending SEL MB1" was detected when the monitor was started (bit 11 of the PC was reset when the monitor was called and set after an unconditional jump instruction was executed), a "SEL MB0" instruction (opcode 0xE5) is inserted in address 0x09.
   If neither a "Pending SEL MB0" nor a "Pending SEL MB1" was detected when the monitor software was started, a "NOP" instruction (opcode 0x00) is inserted in address 0x09.
2. Prepare to restore the timer/counter configuration:
   The opcode for "NOP" (0x00), "STRT T" (opcode 0x55 : start timer/counter as a timer) or "STRT CNT" (opcode 0x45 : start timer/counter as a counter) is stored in address 0x0A, depending on the selection of monitor options in the GUI.
3. Prepare to restore bit0 to bit10 of the PC:
   Addresses 0x0B and 0x0C are loaded with an unconditional jump instruction ("JMP") to the monitor return address reduced by 1 in order to restore bit0 to bit10 of the program counter (PC). The target address entered there must be 1 less than the actual target address in the user program because of the execution of the instruction stored in address 0x0D (see below "Restore the state of the MB flip-flop")!
4. Prepare to restore the MB flip-flop:
   If a "Pending SEL MB0" was detected when the monitor was started (Bit11 of the PC was set when the monitor was called and reset after an unconditional jump instruction was executed), a "SEL MB0" instruction (Opcode 0xE5) is inserted in address 0x0D.
   If a "Pending SEL MB1" was detected when the monitor was started (Bit11 of the PC was reset when the monitor was called and set after an unconditional jump instruction was executed), a "SEL MB1" instruction (Opcode 0xF5) is inserted in address 0x0D.
   If neither a "Pending SEL MB0" nor a "Pending SEL MB1" was detected when the monitor software was started, a "NOP" instruction (Opcode 0x00) is inserted in address 0x0D.

Once the preparations are complete, the loaded program can be executed. The MCS-48 µC controls A0 to A7, D0 to D7, *RAM_OE, *RAM_WE. A8 to A16 are kept at 0x1FE00 by the Debug-µC.

1. Restore PC bit0 to bit11, timer/counter configuration:
   Executing the program from address 0x09 to the command at addresses 0x0B and 0x0C will restore PC bit11 (active memory bank), timer/counter configuration and PC bit0 to bit10.
2. If a new IRQ was detected before executing one of the instructions in addresses 0x09 to 0x0C:
   1. PCL = 0x09
   2. Increment StackPointer in DBG_PSW
   3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
   4. Execute "Restore R0, PSW, T and A" (see 4.3.4)
   5. Execute "Modify Stack" (see 4.1.8)
   6. Re-execute instructions in addresses 0x09 to 0x0C
3. 3. Restore the state of the MB flip-flop:
   As there are no further unconditional jump instructions in the MCS-48 program code, the state of the MB flip-flop can now be restored (otherwise the MB flip-flop would already become effective as bit 11 of the PC) if a "pending bank switch" was detected when the monitor started. To execute the instruction in address 0x0D, the address bus of the MCS-48 µC is separated from the external RAM (bit 0 to bit 10 of the PC already point to the monitor return address reduced by 1), the Debug-µC is used as the source of all address signals and the instruction in address 0x0D (complete: 0x1FE0D) is executed.
4. When executing the command in address 0x0D, there is no detection of an external interrupt request (L level at *INT) if ReturnAddress-1 = 0x003, and there is no detection of a timer/counter interrupt if ReturnAddress-1 = 0x007 (*). This is the only time during the execution of the monitor software when IRQ detection apparently(!) only works to a limited extent (see (*)). If an interrupt was previously detected, the corresponding flag in the Debug-µC is reset in order not to block a possible single-step command from the controlling personal computer.
   If a new IRQ was detected before the command at address 0x0D was executed:
   1. PCL = 0x09
   2. Increment StackPointer in DBG_PSW
   3. If the newly detected IRQ is a timer/counter interrupt, increment DBG_T
   4. Execute "Restore R0, PSW, T and A" (see 4.3.4)
   5. Execute "Modify Stack" (see 4.1.8)
   6. Re-execute instructions in addresses 0x09 to 0x0C
   7. Re-execute instruction in address 0x0D
5. By executing the command at address 0x0D, the PC has adopted the correct value (namely the address of the next command in the MCS-48 user program).

(*) If ReturnAddress-1 = 0x003, then the address of the next instruction to be executed in the user program is 0x004 - the second byte of an ISR for external interrupts (L level at *INT). It is highly unlikely that an external interrupt request should be serviced at this point, even with the most minimalistic ISR (unless the ISR only consists of a "RETR" - but then the whole interrupt makes no sense (see below)):

The detection of external interrupts (L level at *INT) would only fail with the following construction and ReturnAddress=0x004 - and even in this case only if an external interrupt request is generated between the execution of the "JMP ReturnAddress-1" and the last "SEL MBx" command in the monitor software and is only present for a very short time:

Analogous to this for the timer/counter interrupt:

If ReturnAddress-1 = 0x007, then the address of the next command to be executed in the user program is 0x008 - the second byte of an ISR for timer/counter interrupts. It is highly unlikely that a timer/counter interrupt should be serviced at this point, even with the most minimalistic ISR (unless the ISR only consists of a "RETR" - but then the whole interrupt makes no sense (see below)):

The detection of timer/counter interrupts would only fail with the following construction and ReturnAddress=0x008 - and even in this case only if a timer/counter interrupt request is generated between the execution of the "JMP ReturnAddress-1" and the last "SEL MBx" command in the monitor software and is only present for a very short time: