7.0.0 Appendix
7.1.0 Instruction set of 8035,8039,8048,8049,8748,8749,8040,8050 µCs
Mnemonic | Cycles | Bytes | Flags |
ADD A,Rr | 1 | 1 | C |
ADD A,@Ri | 1 | 1 | C |
ADD A,#data | 2 | 2 | C |
ADDC A,Rr | 1 | 1 | C |
ADDC A,@Ri | 1 | 1 | C |
ADDC A,#data | 2 | 2 | C |
ANL A,Rr | 1 | 1 | - |
ANL A,@Ri | 1 | 1 | - |
ANL A,#data | 2 | 2 | - |
ANL BUS,#data | 2 | 2 | - |
ANL Pp,#data | 2 | 2 | - |
ANLD Pp,A | 2 | 1 | - |
CALL address | 2 | 2 | SP |
CLR A | 1 | 1 | - |
CLR C | 1 | 1 | C |
CLR F0 | 1 | 1 | F0 |
CLR F1 | 1 | 1 | F1 |
CPL A | 1 | 1 | - |
CPL C | 1 | 1 | C |
CPL F0 | 1 | 1 | F0 |
CPL F1 | 1 | 1 | F1 |
DA A | 1 | 1 | AC, C |
DEC A | 1 | 1 | - |
DEC Rr | 1 | 1 | - |
DIS I | 1 | 1 | - |
DIS TCNTI | 1 | 1 | - |
DJNZ Rr,address | 2 | 2 | - |
EN I | 1 | 1 | - |
EN TCNTI | 1 | 1 | - |
ENT0 CLK | 1 | 1 | - |
IN A,Pp | 2 | 1 | - |
INC A | 1 | 1 | - |
INC Rr | 1 | 1 | - |
INC @Ri | 1 | 1 | - |
INS A,BUS (*) | 2 | 1 | - |
JBb address | 2 | 2 | - |
JC address | 2 | 2 | - |
JF0 address | 2 | 2 | - |
JF1 address | 2 | 2 | - |
JMP address | 2 | 2 | - |
JMPP @A | 2 | 1 | - |
JNC address | 2 | 2 | - |
JNI address | 2 | 2 | - |
JNT0 address | 2 | 2 | - |
JNT1 address | 2 | 2 | - |
JNZ address | 2 | 2 | - |
JTF address | 2 | 2 | - |
JT0 address | 2 | 2 | - |
Mnemonic | Cycles | Bytes | Flags |
JT1 address | 2 | 2 | - |
JZ address | 2 | 2 | - |
MOV A,#data | 2 | 2 | - |
MOV A,PSW | 1 | 1 | - |
MOV A,Rr | 1 | 1 | - |
MOV A,@Ri | 1 | 1 | - |
MOV A,T | 1 | 1 | - |
MOV PSW,A | 1 | 1 | - |
MOV Rr,A | 1 | 1 | - |
MOV Rr,#data | 2 | 2 | - |
MOV @Ri,A | 1 | 1 | - |
MOV @Ri,#data | 2 | 2 | - |
MOV T,A | 1 | 1 | - |
MOVD A,Pp | 2 | 1 | - |
MOVD Pp,A | 2 | 1 | - |
MOVP A,@A | 2 | 1 | - |
MOVP3 A,@A | 2 | 1 | - |
MOVX A,@Ri | 2 | 1 | - |
MOVX @Ri,A | 2 | 1 | - |
NOP | 1 | 1 | - |
ORL A,Rr | 1 | 1 | - |
ORL A,@Ri | 1 | 1 | - |
ORL A,#data | 2 | 2 | - |
ORL BUS,#data | 2 | 2 | - |
ORL Pp,#data | 2 | 2 | - |
ORLD Pp,A | 2 | 1 | - |
OUTL BUS,A (*) | 2 | 1 | - |
OUTL Pp,A | 2 | 1 | - |
RET | 2 | 1 | SP |
RETR | 2 | 1 | SP, PSW |
RL A | 1 | 1 | - |
RLC A | 1 | 1 | C |
RR A | 1 | 1 | - |
RRC A | 1 | 1 | C |
SEL MB0 | 1 | 1 | - |
SEL MB1 | 1 | 1 | - |
SEL RB0 | 1 | 1 | BS |
SEL RB1 | 1 | 1 | BS |
STOP TCNT | 1 | 1 | - |
STRT CNT | 1 | 1 | - |
STRT T | 1 | 1 | - |
SWAP A | 1 | 1 | - |
XCH A,Rr | 1 | 1 | - |
XCH A,@Ri | 1 | 1 | - |
XCHD A,@Ri | 1 | 1 | - |
XRL A,Rr | 1 | 1 | - |
XRL A,@Ri | 1 | 1 | - |
XRL A,#data | 2 | 2 | - |
(*) Must not be used with an external program memory.
Symbol | Definition |
AC | Auxiliary Carry Flag in PSW |
BS | Bank-Select Flag in PSW |
C | Carry Flag in PSW |
F0 | User Flag 0 in PSW |
F1 | User Flag 1 |
Pp | Port (p = 1, 2 or p = 4...7) |
PSW | Program Status Word |
Ri | Index Register (i = 0, 1) |
Rr | Work Register (r = 0...7) |
SP | Stack-Pointer in PSW |
7.2.0 DeMon48_128k code example "RAM Test"
"RAM Test" for MCS-48 µCs uses the MMU to write to the entire DeMon48_128k RAM, reading back the stored value and comparing it with the previously written value:
- Test memory area 0x1FFFF...0x10000
- Test memory area 0x0FFFF...0x00100
- Copy program from page 0 (start address 0x00000) to page 1 (start address 0x00100)
- Test memory area 0x000FF...0x00000
- Copy program from page 1 (start address 0x00100) to page 0 (start address 0x00000)
If there is a difference between the written and read value, the error-counter output on P1 is incremented. If T0 is set to logic high, the test loop then stops until it is resumed by a high-to-low transition at *INT.
If T1 is set to logic low, an I/O area enabled by the jumper configuration (see "5.0.0 Memory configurations") is disabled via the MMU's expansion register (EXP) before a new test run is started.
;DeMon48_128k RAM Test V1.0.0
;
;Tests its entire 128kB RAM and displays the number of verify errors on P1
;
;T0 : Stop on verify error (1) / Don't stop on verify error (0)
;T1 : Enable (1) / Disable (0) I/O address range
;*INT : Continue after stop (H->L)
;
;2024 M. Schmoll * www.controller-designs.de
;
CPU 8039
ORG 000H
CLR A
OUTL P1,A ;Reset verify errors
RAMTEST128K:
CLR A
JT1 RAMTEST_EXP_WRITE ;Enable I/O, if T1 = 1
MOV A,#00001000B ;Disable I/O, if T1 = 0
RAMTEST_EXP_WRITE:
MOVD P7,A ;EXP = A, DA16 = H
U64K_TEST:
;Test 0x1FFFF...0x10000
MOV R6,#10H
U64K_LOOP2:
MOV A,R6
DEC A
MOVD P5,A ;DBH = A, DA16 = H
MOV R7,#10H
U64K_LOOP1:
MOV A,R7
DEC A
MOVD P4,A ;DBL = A, DA16 = H
CALL TEST256BYT
DJNZ R7,U64K_LOOP1
DJNZ R6,U64K_LOOP2
L64K_TEST:
;Test 0x0FFFF...0x00100
MOV R6,#10H
L64K_LOOP2:
MOV A,R6
DEC A
ORLD P5,A ;DBH = A, DA16 = L
MOV R7,#10H
L64K_LOOP1:
MOV A,R7
DEC A
ORLD P4,A ;DBL = A, DA16 = L
CALL TEST256BYT
MOV A,#02H
XRL A,R7 ;DBL = 0x1 ?
JNZ L64K_CONT
MOV A,#01H
XRL A,R6 ;DBH = 0x0 ?
JZ L64K_EXIT ;Yes, exit before writing to page 0
L64K_CONT:
DJNZ R7,L64K_LOOP1
DJNZ R6,L64K_LOOP2
L64K_EXIT:
;Prepare for 256Byte copy from page 0 to page 1
MOV R7,#01 ;Destination page
MOV R6,#00 ;Source page
CALL COPY256BYT
CPL F0 ;Execute code on page 1
JMP TEST_P0 + 0100H ;Jump to page 1
TEST_P0:
;Test 0x000FF...0x00000
CLR A
ORLD P5,A ;DBH = A, DA16 = L
ORLD P4,A ;DBL = A, DA16 = L
CALL TEST256BYT + 0100 ;Call to page 1
;Prepare for 256Byte copy from page 1 to page 0
MOV R7,#00 ;Destination page
MOV R6,#01 ;Source page
CALL COPY256BYT + 0100 ;Call to page 1
CLR F0 ;Execute code on page 0
JMP RAMTEST128K ;Jump to page 0
;-----------------------------------------------------------------
TEST256BYT:
;Test a 256Byte page selected by DBH and DBL
;Destroys : A,R0,R5,P1
MOV R0,#00
TEST256BYT_L0:
MOV A,R0
CPL A
MOVX @R0,A ;Write
MOVX A,@R0 ;Read
CPL A
XRL A,R0 ;Verify
JZ TEST256BYT_L6 ;Verify ok
IN A,P1 ;Display number of verify errors on P1
INC A
OUTL P1,A
JNT0 TEST256BYT_L5 ;Don't stop on error, if T0 = 0
TEST256BYT_L1:
;Wait for *INT=H
JNI TEST256BYT_L1
MOV R5,#00H ;Debounce
NOP
NOP
NOP
DJNZ R5,$-3
TEST256BYT_L2:
;Wait for *INT=L
JNI TEST256BYT_L5
TEST256BYT_L3:
JF0 TEST256BYT_L4 ;F0 is set, if code is on page 1
JMP TEST256BYT_L2 ;Jump to page 0
TEST256BYT_L4:
JMP TEST256BYT_L2 + 0100H ;Jump to page 1
TEST256BYT_L5:
MOV R5,#00H ;Delay after verify error
NOP
NOP
NOP
DJNZ R5,$-3
TEST256BYT_L6:
DJNZ R0,TEST256BYT_L0
RET
;-----------------------------------------------------------------
COPY256BYT:
;Copy a 256Byte page in 4kB-Bank 0
;R7 = Destination page
;R6 = Source page
;Destroys : A,R0,R5,DBL,DBH,DA16
CLR A
ORLD P5,A ;DBH = A, DA16 = L
MOV R0,A ;Init loop counter
COPY256BYT_L:
MOV A,R6 ;Source page
ORLD P4,A ;DBL = A, DA16 = L
MOV A,R0
MOVX A,@R0
MOV R5,A
MOV A,R7 ;Destination page
ORLD P4,A ;DBL = A, DA16 = L
MOV A,R5
MOVX @R0,A
DJNZ R0,COPY256BYT_L
RET
DeMon48_128k_Documentation - Online version - ©2023,2024 Marco Schmoll *
www.controller-designs.de * All Rights Reserved !
DeMon48_128k * Intel 8049 / MCS-48 Hardware-Debugger & Monitor - ©2021...2024 Marco Schmoll *
www.controller-designs.de * All Rights Reserved !