DeMon48_128k

    ;DeMon48_128k RAM Test V1.1.0
    ;
    ;Tests its entire 128kB RAM 256 times and displays the number of verify
    ;errors or test runs on P1 and various status signals on P2.7 ... P2.5
    ;
    ;V1.0.0 Inital release
    ;V1.0.1 Uses a more sophisticated test pattern by toggling
    ;       inversion of the written value every 256 bytes and between
    ;       successive runs
    ;V1.1.0 Improved test pattern, status displays on P2 and error / test
    ;       counter display on P1
    ;
    ;(c)2024 M. Schmoll * www.controller-designs.de
    ;
    ;T0   : 1=Stop on verify error / 0=Don't stop on verify error
    ;T1   : 1=Enable I/O address range / 0=Disable I/O address range
    ;*INT : Continue after stop (H->L)
    ;P2.7 : Test is complete (Output)
    ;P2.6 : Stopped after error (Output)
    ;P2.5 : Error(s) detected (Output)
    ;P2.4 : 1=Display test counter, 0=Display error counter (Input)
    ;R7 : Loop counter (DBL)
    ;R6 : Loop counter (DBH)
    ;R5 : Temporary register
    ;R4 : Test counter
    ;R3 : Error counter
    CPU 8039
    ORG 000H
    CLR A
    MOV R4,A            ;Initialize Test counter
    MOV R3,A            ;Initialize Error counter
    ORL A,#00010000B    ;P2.4 = Input
    OUTL P2,A
RAMTEST128K:
    CALL READ_SWITCHES_AND_DISPLAY
    CLR A
    JT1 RAMTEST_EXP_WRITE ;Enable I/O, if T1 = 1
    MOV A,#00001000B    ;Disable I/O, if T1 = 0
RAMTEST_EXP_WRITE:
    MOVD P7,A           ;EXP = A, DA16 = H
U64K_TEST:
    ;Test 0x1FFFF...0x10000
    MOV R6,#10H
U64K_LOOP2:
    MOV A,R6
    DEC A
    MOVD P5,A           ;DBH = A, DA16 = H
    MOV R7,#10H
U64K_LOOP1:
    MOV A,R7
    DEC A
    MOVD P4,A           ;DBL = A, DA16 = H
    CALL TEST256BYT
    CALL READ_SWITCHES_AND_DISPLAY
    DJNZ R7,U64K_LOOP1
    DJNZ R6,U64K_LOOP2
L64K_TEST:
    ;Test 0x0FFFF...0x00100
    MOV R6,#10H
L64K_LOOP2:
    MOV A,R6
    DEC A
    ORLD P5,A           ;DBH = A, DA16 = L
    MOV R7,#10H
L64K_LOOP1:
    MOV A,R7
    DEC A
    ORLD P4,A           ;DBL = A, DA16 = L
    CALL TEST256BYT
    CALL READ_SWITCHES_AND_DISPLAY
    MOV A,#02H
    XRL A,R7            ;DBL = 0x1 ?
    JNZ L64K_CONT
    MOV A,#01H
    XRL A,R6            ;DBH = 0x0 ?
    JZ L64K_EXIT        ;Yes, exit before writing to page 0
L64K_CONT:
    DJNZ R7,L64K_LOOP1
    DJNZ R6,L64K_LOOP2
L64K_EXIT:
    ;Prepare 256Byte copy from page 0 to page 1
    MOV R7,#01          ;Destination page
    MOV R6,#00          ;Source page
    CALL COPY256BYT
    JMP TEST_P0 + 0100H ;Jump to page 1
TEST_P0:
    ;Test 0x000FF...0x00000
    CLR A
    ORLD P5,A           ;DBH = A, DA16 = L
    ORLD P4,A           ;DBL = A, DA16 = L
    CALL TEST256BYT + 0100H ;Call to page 1
    CALL READ_SWITCHES_AND_DISPLAY + 0100H
    ;Prepare 256Byte copy from page 1 to page 0
    MOV R7,#00          ;Destination page
    MOV R6,#01          ;Source page
    CALL COPY256BYT + 0100H ;Call to page 1
    CPL F0              ;Toggle invert/non-invert bit for next run
    DJNZ R4,RAMTEST128K_NEXT
RAMTEST128K_FINISH:
    IN A,P2             ;Set "Test finished" output
    ORL A,#10010000B
    OUTL P2,A
RAMTEST128K_FINISH_L0:
    CALL READ_SWITCHES_AND_DISPLAY
    JMP RAMTEST128K_FINISH_L0
RAMTEST128K_NEXT:
    JMP RAMTEST128K     ;Jump to page 0
    ;------------------------------------------------------------------------
TEST256BYT:
    ;Test a 256Byte page selected by DBH and DBL
    ;Destroys : A,R0,R5,P1
    MOV R0,#00
TEST256BYT_L0:
    MOV A,R0
    JF0 TEST256BYT_L1
    CPL A               ;Invert write value, if F0 = 0
TEST256BYT_L1:
    ADD A,R4            ;Add Test counter value
    MOV R5,A            ;Save write value
    MOVX @R0,A          ;Write
    MOVX A,@R0          ;Read
    XRL A,R5            ;Verify
    JZ TEST256BYT_L5    ;Verify ok
    INC R3              ;Increment Error counter
    IN A,P2             ;Set "Error(s) detected" output
    ORL A,#00110000B
    OUTL P2,A
    CALL READ_SWITCHES_AND_DISPLAY
    JNT0 TEST256BYT_L4  ;Don't stop on error, if T0 = 0
    IN A,P2             ;Set "Test stopped" output
    ORL A,#01010000B
    OUTL P2,A
TEST256BYT_L2:
    ;Wait for *INT=H
    CALL READ_SWITCHES_AND_DISPLAY
    JNI TEST256BYT_L2
    MOV R5,#00H         ;Debounce
    NOP
    NOP
    NOP
    DJNZ R5,$-3
    CLR C
TEST256BYT_L3:
    ;Wait for *INT=L
    CALL READ_SWITCHES_AND_DISPLAY
    JNI TEST256BYT_L4
    JNC TEST256BYT_L3
TEST256BYT_L4:
    MOV R5,#00H         ;Delay after verify error
    NOP
    NOP
    NOP
    DJNZ R5,$-3
    IN A,P2             ;Clear "Test stopped" output
    ANL A,#10111111B
    ORL A,#00010000B    ;P2.4 = Input
    OUTL P2,A
TEST256BYT_L5:
    DJNZ R0,TEST256BYT_L0
    CPL F0              ;Toggle invert/non-invert bit for next 256 bytes
    RET
    ;------------------------------------------------------------------------
COPY256BYT:
    ;Copy a 256Byte page in 4kB-Bank 0
    ;R7 = Destination page
    ;R6 = Source page
    ;Destroys : A,R0,R5,DBL,DBH,DA16
    CLR A
    ORLD P5,A           ;DBH = A, DA16 = L
    MOV R0,A            ;Init loop counter
COPY256BYT_L:
    MOV A,R6            ;Source page
    ORLD P4,A           ;DBL = A, DA16 = L
    MOV A,R0
    MOVX A,@R0
    MOV R5,A
    MOV A,R7            ;Destination page
    ORLD P4,A           ;DBL = A, DA16 = L
    MOV A,R5
    MOVX @R0,A
    DJNZ R0,COPY256BYT_L
    RET
    ;------------------------------------------------------------------------
READ_SWITCHES_AND_DISPLAY:
    ;P2.4 : 1=Display test counter, 0=Display error counter (Input)
    ;R4 : Test counter
    ;R3 : Error counter
    IN A,P2
    ANL A,#00010000B
    JZ READ_SWITCHES_AND_DISPLAY_L
    MOV A,R4            ;Test counter
    CPL A
    INC A
    OUTL P1,A
    RET
READ_SWITCHES_AND_DISPLAY_L:
    MOV A,R3            ;Error counter
    OUTL P1,A
    RET